1. Field of the Invention
The present invention relates to memory cell and, more particularly, to a dynamic random access memory (DRAM) cell having a deep trench capacitor and a vertical transistor. The vertical transistor has a channel region that surrounds the sidewall and top of a control gate electrode to provide sufficient channel length and decrease leakage current.
2. Description of the Related Art
There is much interest in reducing the size of individual semiconductor devices to increase their density on an integrated circuit (IC) chip. This reduces size and power consumption of the chip, and allows faster operation of the chip. In order to achieve a memory cell with a minimum size, the gate length in a conventional transistor must be reduced to decrease the lateral dimension of the memory cell. However, the shorter gate length will result in higher leakage currents that cannot be tolerated, and the voltage on the bit line must therefore also be scale down. This reduces the charges stored on a storage capacitor, and thus requires a larger capacitance to ensure that stored charges are sensed correctly.
In order to solve the above-mentioned problems, a stacked capacitor and a deep trench capacitor have been developed for a high-integration memory cell, such as dynamic random access memory (DRAM) cell. Especially, the deep trench capacitor is formed in a deep trench within the silicon substrate, thus the capacitor storage region cannot consume any additional wafer area. In addition, a vertical transistor has recently been developed which can maintain the gate length at a suitable value for obtaining low leakage, without decreasing the bit line voltage or increasing the memory cell""s lateral dimension.
A type of vertical transistor with a deep trench capacitor is disclosed in U.S. Pat. No. 6,034,389. As shown in FIG. 1, a P-type silicon substrate 10 comprises a plurality of deep trenches 11 and a plurality of pillars 12 corresponding to the deep trenches 11. In the lower region of the deep trench 11, an n+-type diffusion region 13 is formed on the sidewall of the pillar 12 to serve as a source region of a vertical transistor and a storage node of a deep trench capacitor, a p+-type electric-field isolating region 14 formed on the bottom of the deep trench 11 to ensure an appropriate isolation between the adjacent n+-type diffusion regions 13, an ONO thin film 15 formed on the sidewall of the deep trench 11 to serve as a capacitor dielectric of the deep trench capacitor, and an n+-type polysilicon layer 16 fills the lower region of the deep trench 11 to serve as an electrode plate of the deep trench capacitor.
In the upper region of the deep trench 11, a barrier oxide layer 17 covers the top of the n+-type polysilicon layer 16, two n+-type polysilicon layers 19 patterned as two adjacent word lines are formed on the barrier oxide layer 17 to serve as two control gate electrodes, a gate oxide layer 18 is formed on the sidewall of the deep trench 11 to surround the control gate electrodes 19, an n+-type diffusion region 20 is formed on the top of the pillar 12 to serve as a drain region of the vertical transistor, and a metal layer 22 is formed over the vertical transistor and perpendicular to the word lines to serve as a bit line.
According the above-described memory cell, the n+-type polysilicon layers 19, the n+-type diffusion region 13 and the n+-type diffusion region 20 form the vertical transistor, and the n+-type diffusion region 13, the ONO thin film 15 and the n+-type polysilicon layers 16 form the deep trench capacitor. In an open bit line case as described, the storage node of the deep trench capacitor is common to all the memory cells in the array, and the charge is stored on the n+-type diffusion region 13 within each pillar 12. In addition, a channel region 24 between the n+-type diffusion regions 13 and 20 is formed on the sidewall of the pillar 12 to serve as a strip-shaped channel of the vertical transistor.
In order to prevent leakage current in the OFF state, a sufficient length of the channel region 24 is required. One method of achieving this is to fabricate the deep trench 11 with a greater depth, but the depth is restricted by process limitations. The other way is to adjust the size ratio of the deep trench capacitor to the vertical transistor within the deep trench 11, but this creates difficulties in tuning electrical performance.
The present invention provides a DRAM cell having a deep trench capacitor and a vertical transistor, in which a channel region has sufficient length to reduce leakage current.
The DRAM cell is formed on a substrate having a plurality of deep trenches arranged in array. Within each deep trench, a deep trench capacitor is formed with a storage node formed in the substrate and surrounding the deep trench, a capacitor dielectric is formed on the sidewall of the deep trench, and an electrode plate fills the deep trench. An isolating layer covers the deep trench capacitor and has a first contact hole to expose a predetermined region of the electrode plate, wherein the exposed region of the electrode plate is a first doped region. A control gate electrode is patterned on the isolating layer over the deep trench capacitor, wherein the first doped region is formed at one side of the control gate electrode. A gate insulating layer covers the sidewall and top of the control gate electrode. A well Si layer covers the isolating layer, the gate insulating layer and the exposed electrode plate to fill the first contact hole. The well Si layer comprises a second doped region formed at the other side of the control gate electrode.
Accordingly, it is a principal object of the invention to provide the deep trench arranged in array and having a large lateral size.
It is another object of the invention to provide the deep trench capacitor below the vertical transistor without consuming lateral size of the DRAM cell.
Yet another object of the invention is to provide a channel region surrounding the sidewall and top of the control gat electrode.